The present disclosure relates to testing integrated circuits and to scan-based testing of integrated circuits.
The use of scan-based techniques for testing integrated circuits (ICs) has become essential as IC component (e.g., transistor) density has increased. One reason for this is that due to size constraints, component density has far outstripped the number of electrical connectors, typically referred to as input/output pins, capable of being built into an IC. Thus, a circuit tester testing IC fuinctionality via a limited number of pins encounters increasing difficulty in adequately reaching the voluminous number of state permutations and transitions provided by increased integration. As a result, modern ICs are typically equipped with scannable logic Ielements to facilitate testing. A typical scannable IC includes one or more sets of state-holding elements (registers) interposed between circuit components and/or between circuit components and input/output pins. During normal operation, the state-holding elements are transparent to or incorporated as part of the fuinctionality of the IC; in test mode, they are configurable as a serial shift register, or xe2x80x9cscan-chain,xe2x80x9d typically by linking the output of one state-holding element to the input of another. The xe2x80x9cscan-chainxe2x80x9d permits scan test data to be serially shifted into and out of the state-holding elements via one or more input/output pins, thereby increasing the states reachable by a tester. Strategically placed scan-chains also enable a tester to target one or more internal modules (e.g., a functional grouping of transistors) for individualized testing; in these situations, typically only a portion of the scan-chain needed to complete the test is filled with scan-data. Currently, the number and length of scan-chains vary per the device, but typically range in number between twenty and one-hundred, and in length upward of a thousand or more interconnected state-holding elements. Many devices with a single scan-chain have been fabricated.
In a typical circuit test, a tester applies digital signal patterns to the pins of a device under test (xe2x80x9cDUTxe2x80x9d). The content, sequence and timing of test patterns are dependent on the architecture of the particular DUT, and are typically generated by the DUT manufacturer with the IC design software used for designing the DUT. There are two predominant types of test patterns used in the prior art: scan test patterns and functional test patterns. Scan test patterns are bit patterns used to test selected states in a DUT""s scan-chain; functional patterns are bit patterns typically applied in parallel to the input pins on the DUT to test functionality at the pin level. There are three predominant types of scan test patterns in the prior art: a scan-in pattern, a scan-out pattern and a scan-mask pattern. The scan-in pattern is the bit sequence serially shifted into a scan-chain to configure the IC to a known starting state. The scan-out pattern is the bit sequence containing the expected states in a scan-chain resulting from the DUT""s processing the scan-in pattern. The scan-mask pattern is a bit pattern used for filtering out states to be ignored in a particular test.
The steps in a typical scan test iteration are as follows: 1) the tester places the DUT in scan-test mode to configure the scannable logic into a scan-chain; 2) the tester serially shifts a scan-in pattern into the scan-chain with a scan clock via one or more DUT pins; 3) the tester switches the DUT to normal mode and applies one or more system clock signals to the DUT in combination with one or more ftmctional patterns on the DUT input pins; 4) the DUT processes the test states in the scan-chain and the input pins; 5) the tester tests the states on the output pins, then switches the DUT back to scan-test mode; 6) the tester serially clocks out the states of the scan-chain with a scan clock for comparison with a scan-out pattern containing the expected results, ignoring states as indicated by the scan-mask pattern; and 7) the tester serially shifts in a new scan-in pattern with the scan clock, and repeats the above steps.
In the prior art, a xe2x80x9cmonolithicxe2x80x9d approach for storing and processing scan patterns predominates. In this approach, all of the scan patterns used in a test sequence are typically stored in sequential order in a contiguous block of tester memory in bit lengths corresponding in length to the scan-chains they are designed to populate. Thus, the tester need only know the start address of the contiguous block of scan patterns to complete a scan test sequence on a DUT, and scan data controllers are typically limited in data retrieval to a straight-line method, i.e., they are only capable of retrieving words of data in a monolithic sequence. There are a number of inefficiencies encountered by this approach. First, modem DUT""s may implement scan-chains of considerable length where only a specific sub-section of a scan-chain needs populating for a particular test. In a monolithic approach, a block of scan memory corresponding to the length of the scan-chain must be populated regardless of whether only a portion of the scan-chain is to be populated; this creates unused space (xe2x80x9cdead spacexe2x80x9d) in the memory before and after the relevant portion of scan data (the dead space is typically filled with xe2x80x9cdummy dataxe2x80x9d consisting of pads of zeros). Dead space is costly due to the large memory requirements of a tester and the potentially large scan-chains employed; for example, modem testers may employ several dozen pins participating in a test of several tens of thousands of test patterns involving scan-chains with a depth of over a thousand state-holding elements. Second, particular scan patterns in a test sequence may be repeated. In the monolithic approach, said particular scan patterns must be written into memory each time they appear in the sequence, thus creating the possibility of data redundancy. Lastly, it is often desirable to re-sequence scan patterns into new test sequences. In the monolithic approach, which lacks any level of indirection, re-sequencing requires that an entirely new test sequence be created and downloaded as a block into a contiguous portion of memory. This introduces excessive complexity and processing time for test re-sequencing.
The present disclosure is directed to apparatus and methods for, among other things, minimizing scan memory requirements for scan testers, re-sequencing scan tests efficiently, and interleaving scan data to save testing time. In one embodiment, an apparatus and method are provided for improving the storage and processing of scan data by enabling scan data to be stored in scan memory without the substantial dummy data sequences that are typical in xe2x80x9cmonolithicxe2x80x9d scan testing and storage techniques; this is achieved by storing non-dummy scan data (xe2x80x9cscan data segmentsxe2x80x9d) in separate segments in scan memory. Processing scan data segments is controlled by scan data segment pointers organized in a link table data structure (xe2x80x9clink tablexe2x80x9d). In another embodiment, each scan data segment pointer is allocated a separate row in the link table. This method of storage enables the amount of scan memory to be substantially reduced, saving testing cost. In addition, scan data re-sequencingxe2x80x94which in typical xe2x80x9cmonolithicxe2x80x9d scan techniques required the scan data itself to be entirely re-sequenced and re-written in the scan memoryxe2x80x94may now be performed by re-sequencing pointer data in the link table; thus, only link tables and associated data need to be re-sequenced and re-written into a memoryxe2x80x94not the scan data itselfxe2x80x94resulting in savings in testing time and cost. In another embodiment, a method is provided enabling (variable length) scan data segments to be interleaved during testing; this is achieved by delaying the processing of each scan data segment according to a pre-determined delay value. A method is provided for calculating delay values which optimizes the amount of scan data that may be simultaneously processed. Interleaving the scan data while conducting a scan test saves testing time, and therefore testing cost.
In some embodiments, a scan-data-immediate flag is associated with a scan data segment pointer which, if set, changes the mode in which link table data is processed. If the scan-data-immediate flag is set, stream controllers process link table rows as having two fields: a data field and a counter field. The data field contains the scan data segment itself, in contrasts to a pointer to the scan data segment in memory, and a counter field containing a repeat value for how often the scan data segment is to be consecutively processed when scanned out by the stream controllers. Scan-data-immediate processing enables a scan-memory retrieval operation to be avoided, therefore saving scan processing cost and time. In another embodiment, a link table row contains a scan-disable flag which, if set, prevents data from being driven to the respective DUT pin during the processing of that row. In another embodiment, setting the scan-disable flag prevents data from being driven to the DUT pin for the remainder of the scan stream. Disabling scan data from certain DUT pins is sometimes useful to prevent excessive heat accumulation in the DUT; excessive heat may damage the DUT or lead to erroneous test results. Disabling scan data from certain DUT pins may also be useful when concentrating a scan test to a particular portion of the device, thus saving data analysis time.